Power high frequency devices have been built using a variety of semiconductor technologies. For a long time the preferred vehicle for their realization has been the NPN bipolar junction transistor (BJT). Its primary advantage was the achievable high intrinsic transconductance (g.sub.m) that permitted the fabrication of high power devices utilizing small silicon areas.
As processing technology improved, in the early 1970's a number of MOSFET vertical structures begun to challenge the dominance of the BJT at the lower RF frequencies, trading the cost of the large silicon area, necessary to provide the current capability in MOSFETs, for the cost of simple processing. The advantages that the MOSFET structure provided to the user were: higher power gain, ruggedness (defined as the capacity to withstand transients) and ease of biasing.
In the continuous quest for high frequency operation at high power the MOSFET structure has displaced the BJT since the early 1970's in applications where its performance has been competitive.
Recently, new prior art RF MOS devices have been placed on the market by several vendors. The new prior art RF MOS devices utilize the standard lateral MOS device with a diffused via that connects the source to the backside of the chip such that the back side becomes both electrical and thermal ground. The prior art structure also uses a polysilicide gate process as a compromise between the fabrication benefits of the self aligned polysilicon gate and the high frequency performance of the metal gate structure. The prior art structure has extended the frequency of operation of MOS devices into the 2 GHz region thus covering two frequency bands of great commercial importance: the cellular and PCS/PCN mobile telephone bands.
The via backside contact design and the polysilicide gate processing technology have allowed the prior art device to attain its performance. Firstly, by transferring the source connection to the backside of the chip through a diffused via, the packaging of the device has been simplified reducing parasitic inductance and resistance to ground. The thermal dissipation has been also improved because an electrical isolation layer in the package has been removed. Secondly, the output capacitance of RF MOS device for the common-source mode of amplification operation has been made comparable to the output capacitance obtained with BJT structures. This results in improved collector efficiency and in wider usable bandwidth (BW) of the RF MOS device operating as an amplifier. This improvement comes about as the lateral RF MOS device at high drain-source applied bias has a lower drain-source capacitance (C.sub.ds) than the drain-source capacitance of the prior art RF MOS devices. Finally, the use of polysilicide allows the efficient feeding of long gate fingers.
The design of the existing lateral RF MOS devices was further improved in the lateral RF MOS device disclosed in the U.S. Pat. No. 5,949,104, issued on Sep. 7, 1999 and incorporated by reference herein in its entirety. In the '104 patent the connection from the source to the backside of the silicon substrate was improved by using a metal plug. The usage of the metal plug to connect the source to the backside of the silicon substrate further reduced the space needed for that connection, and eliminated the lateral as well as the downward movement of the source to backside via diffusion. The metal plug design allowed the inclusion of more usable device active area per unit chip area, lead to an increase of available device output power per unity chip area, resulted in a further decrement of the minimal value of the drain-source capacitance (C.sub.ds), and in a wider usable BW of the device operating as an amplifier.
Prior art lateral RF MOS devices have an inadequate maximum density of current that could flow in the source-drain channel due to a low breakdown voltage. Indeed, dimensions of the source-drain channel are limited by the size of the lateral RF MOS device. The increased breakdown voltage would allow higher current density to flow in the source-drain channel thus increasing the power that could be dissipated at the lateral RF MOS device of the same size.
The patent application Ser. No. 09/413,912, entitled "LATERAL RF MOS DEVICE WITH IMPROVED BREAKDOWN VOLTAGE", filed on the same date as the present patent application, and assigned to the same assignee as the present patent application, is incorporated herein in its entirety and is referred to as the patent application #1.
The patent application #1 addresses the problem of inadequate maximum density of current that could flow in the source-drain channel due to a low breakdown voltage in a prior art lateral RF MOS by including two drain drift regions with different concentrations of carriers in the source-drain current channel.
However, a prior art lateral RF MOS device is difficult to use as a power amplifier with sufficient bandwidth (BW) to cover the high frequencies (900 MHZ -2 GHz) that are important for wireless applications. This is due to the fact that a prior art lateral RF MOS device has a too high output drain-source capacitance.
Thus, what is needed is to improve the design of a prior art lateral RF MOS device which would lead to a lateral RF MOS device having the prior art size but a decreased drain-source capacitance.